In a conventional method for fabricating a semiconductor device, an about 10 nm-thick pad oxide film is formed on a silicon substrate, and an about 200 nm-thick silicon nitride film is then formed by CVD (chemical vapor deposition). The whole surface of the silicon nitride film is coated with a photoresist, and the photoresist is patterned in accordance with a field pattern by photolithography. Next, the silicon nitride film is selectively etched using the photoresist as the mask, and the photoresist is removed, followed by thermal oxidation in a water vapor atmosphere to form a field oxide film. The silicon nitride film and the pad oxide film are then removed, a gate oxide film is formed, gate polysilicon is grown on the whole surface of the gate oxide film and the field oxide film, and the gate polysilicon is doped with an impurity by ion implantation or diffusion. A photoresist is coated on the whole surface of the gate polysilicon, and the photoresist is patterned in accordance with a gate pattern by photolithography. In the patterning of the photoresist, registration with the underlying field pattern is carried out. Next, the gate polysilicon is selectively etched using the photoresist as a mask, and the resist is removed to form gate electrodes. The gate electrode may be a single polysilicon layer as adopted in this method, or alternatively may have a polycide structure wherein a silicide is stacked on polysilicon. Further, subsequent ion implantation into source/drain may serve also as the doping of the gate polysilicon.
In the conventional method for fabricating a semiconductor device, however, misregistration is created in registration for the later step with respect to the underlying field pattern, for example, registration between the gate pattern and the field pattern. This is because the silicon nitride film has strong tensile stress and causes shrinkage of wafer. Specifically, the resist patterning for the field is carried out on a silicon substrate shrunken by tensile stress. When the silicon nitride film is removed after the formation of the field oxide film, the silicon substrate is in a stretched state as compared with the time when the resist patterning of the field has been performed. Therefore, the field pattern is larger than the original size. Since the underlying field pattern is larger than the original size, misregistration attributable to a difference in dimension between the field and the gate is created at the time of forming a resist pattern for the gate in a later step. The larger the size of the chip and consequently the smaller the minimum fabrication dimension, the larger the influence of misregistration at the time of registration/exposure attributable to the shrinkage of the wafer created by the stress. In order to alleviate this problem, Eer Nisse et al., Journal of Applied Physics, vol. 48, No. 8 (1977), pp. 3337-3341 discloses that the stress of the nitride film can be reduced by ion implantation in the vicinity of the interface of the nitride film and the substrate silicon under such conditions that the projected range is rendered identical. The ion implantation in this way however, causes about half of the injected ions to penetrate into the silicon substrate. These ions which have penetrated into the silicon substrate create defects in the silicon substrate. The defects lead to problems, for example, leak current and deteriorated proof voltage in a completed device.
Japanese Patent Laid-Open No. 36935/1980 discloses that ion implantation into a silicon nitride film at a high dose of 1.times.10.sup.15 to 1.times.10.sup.17 cm.sup.-2 results in lowered stress. Long ion implantation time is necessary for the ion implantation at such a high dose, leading to lowered productivity, which is unsuitable for practical use. Further, although ion implantation into the silicon nitride film is described, this publication is silent on conditions under which the ions should be implanted into the film. Therefore, here again the above problems are likely to occur.
The present inventor has made detailed studies on the relationship between the conditions for the ion implantation and the stress of the silicon nitride film and as a result has found that careful selection of the ion implantation energy can effectively reduce the stress of the silicon nitride film, unlike the prior art technique, without penetration of injected ions into the silicon substrate to deteriorate the device properties and without lowering productivity.